1. Field of the Invention
Generally, the present disclosure relates to the field of fabricating microstructures, such as integrated circuits, and, more particularly, to the handling of substrates in process tools, such as cluster tools, used for the fabrication of semiconductor devices or other microstructures.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of microstructure fabrication, for instance for manufacturing semiconductor devices, since, in this field, it is essential to combine cutting-edge technology with mass production techniques. It is, therefore, the goal of manufacturers of semiconductors or generally of microstructures to reduce the consumption of raw materials and consumables while at the same time improving process tool utilization. The latter aspect is especially important since, in modern semiconductor facilities, equipment is required which is extremely cost intensive and represents the dominant part of the total production costs. At the same time, the process tools of the semiconductor facility have to be replaced more frequently compared to most other technical fields due to the rapid development of new products and processes, which may also demand correspondingly adapted process tools.
Integrated circuits are typically manufactured in automated or semi-automated facilities, thereby passing through a large number of process and metrology steps to complete the device. The number and the type of process steps and metrology steps a semiconductor device has to go through depends on the specifics of the semiconductor device to be fabricated. A usual process flow for an integrated circuit may include deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like, in combination with a plurality of photolithography steps to image a circuit pattern for a specific device layer into a resist layer, which is subsequently patterned to form a resist mask for further processes in structuring the device layer under consideration by, for example, etch or implant processes and the like. Thus, layer after layer, a plurality of process steps are performed based on a specific lithographic mask set for the various layers of the specified device. For instance, a sophisticated CPU requires several hundred process steps, each of which has to be carried out within specified process margins to fulfill the specifications for the device under consideration. As the majority of the process margins are device specific, many of the metrology processes and the actual manufacturing processes are specifically designed for the device under consideration and require specific parameter settings at the adequate metrology and process tools.
In a semiconductor facility, a plurality of different product types are usually manufactured at the same time, such as memory chips of different design and storage capacity, CPUs of different design and operating speed and the like, wherein the number of different product types may even reach hundreds and more in production lines for manufacturing ASICs (application specific ICs). Since each of the different product types may require a specific process flow, possibly based on different mask sets for the lithography, specific settings in the various process tools, such as deposition tools, etch tools, implantation tools, chemical mechanical polishing CMP) tools and the like, may be necessary. Consequently, a plurality of different tool parameter settings and product types may be encountered simultaneously in a manufacturing environment.
Hereinafter, the parameter setting for a specific process in a specified process tool or metrology or inspection tool may commonly be referred to as process recipe or simply as recipe. Thus, a large number of different process recipes, even for the same type of process tools, may be required which have to be applied to the process tools at the time the corresponding product types are to be processed in the respective tools. However, the sequence of process recipes performed in process and metrology tools or in functionally combined equipment groups, as well as the recipes themselves, may have to be frequently altered due to fast product changes and highly variable processes involved. As a consequence, the resulting tool performance obtained for the various process recipes, especially in terms of throughput, is a very critical manufacturing parameter as it significantly affects the overall production costs of the individual devices.
Currently, very complex process tools, referred to as cluster or cluster tools, are increasingly being used. These cluster tools may include a plurality of functional modules and entities with a plurality of process chambers, which may be operated in a parallel and/or sequential manner such that products arriving at the cluster tool may be processed therein in a plurality of process paths, depending on the process recipe and the current tool state. The cluster tool may enable the performance of a sequence of correlated processes, thereby enhancing overall efficiency by, for instance, reducing transport activities within the factory. Furthermore, the cluster tools allow increased tool capacity and availability by using several process chambers in parallel for the same process step.
In a cluster tool, several process chambers are typically served by one robot substrate handler, wherein, typically, process chambers of each process step, which may involve the operation of two or more parallel process chambers, may be accomplished such that a maximum overall throughput of the cluster tool is accomplished. For example, a frequently used rule for operating the cluster tool is adjusted such that the sequencing provides a substantially continuous supply of substrates to the “bottleneck” process step, i.e., to the process chambers of a specific process step having the least process capacity, since otherwise an idle process time at the bottleneck step may significantly affect the overall throughput of the cluster tool. Although overall enhanced performance in view of process quality and throughput may be accomplished by integrating a plurality of correlated process steps into a cluster tool, in which at least some of the correlated process steps may be performed in parallel, a complex mutual interaction of the various process chambers may determine the actual throughput behavior over time. For example, the various process chambers in the cluster tool may require maintenance activities on a regular basis, for instance based on a predetermined wafer processing capability, which may affect the overall throughput. Typically, the various process steps may be performed in parallel so that a failure or a maintenance activity in one of the parallel process chambers may not result in a complete non-productive time of the cluster tool, but may affect the throughput according to the percentage of the total over processing capacity of the process chamber under consideration. Consequently, upon performing a planned maintenance activity on one process chamber of a corresponding process step, one or more other process chambers used in this process step may still process substrates, however, at a reduced overall throughput of the cluster tools, since the over-processing capacity of each of the process chambers may be less than 100% of the throughput of the cluster tool when considered as a whole. Consequently, any down times of any of the process chambers may affect the overall throughput of the cluster tool, depending on the dedicated wafer processing capacity of the known productive process chamber, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cluster tool 100, which may comprise a main frame 101, which may be considered as an appropriate mechanical system for accommodating the components of the cluster tool 100, such as process chambers, electronic components, mechanical components, supply lines for process gases, a transport interface for exchanging substrates with a manufacturing environment, such as a semiconductor production facility, and the like. Thus, in the main frame 101, one or more load ports 102 may be provided to provide the required substrate exchange capability with a manufacturing environment. As is well known, typically, substrates, such as wafers, may be handled on the basis of appropriate transport carriers, such as front opening unified pods (FOUP), as indicated by 102A, in which a corresponding number of substrates 104 may be supplied to and discharged from the cluster tool 100. Furthermore, the cluster tool 100 comprises a device internal transport system, such as a robot handler and the like, 103, which is operatively connected to the one or more load ports 102 and to a plurality of process chambers 110. In the example shown, the plurality of process chambers 110 may be functionally grouped into three process steps, S1, S2, S3, wherein each process step may represent a specific type of process, such as the deposition of a material layer, a surface treatment, an anneal process and the like, as required for obtaining a specific process result for substrates stepped through the cluster tool 100. For example, step S1 may be associated with two process chambers, 111A, 111B which may be considered as parallel process chambers, since the same process corresponding to step S1 is performed in any of the chambers 111A, 111B. Similarly, the process step S2 may be associated with two process chambers 112A, 112B, which perform the same process steps within the sequence of correlated process steps S1, S2, S3. Finally, the step S3 may be associated with process chambers 113A, 113B which may represent the final process step of the sequence of correlated process steps represented by the process steps S1, S2 and S3. It should be appreciated that more or less process steps may be incorporated into the overall process sequence performed within the cluster tool 100, wherein, in each step, more than two process chambers may be used, while, in some process steps, a single process chamber may be provided, if a certain degree of redundancy may be considered inappropriate.
The tool internal transport system 103, in combination with a tool internal arrangement of the process chambers 110, is configured such that the substrates 104 obtained from the load port 102 can be distributed to the process chambers 110 according to the sequence of process steps S1, S2, S3, wherein the substrates within a single process step may be distributed among the corresponding process chambers in accordance with the availability of each process chamber. That is, typically, the transport system 103 may, for the arrangement shown in FIG. 1a. deliver substrates in an alternating manner.
FIG. 1b schematically illustrates the cluster tool 100 during operation. As illustrated, the substrate 104 may be supplied to the process chambers 111A, 111B of the first step by the tool internal transport system 103, typically in an alternating manner. After completing the process step S1, the substrate is supplied to any of the process chambers 112A, 112B, depending on the current availability of these process chambers, which is also typically to be performed in an alternating manner, if each process chamber is in a productive state. Similarly, the substrates processed in the chambers 112A, 112B may be supplied to the process chambers 113A, 113B depending on the current availability of these chambers, wherein, typically, the process chambers 113A, 113B may also be supplied in an alternating manner. Consequently, if all process chambers 110 are in an operable state, the overall throughput of the cluster tool 100 may be determined by that process step S1, S2, S3 which may have the least wafer processing capacity, wherein it should be appreciated that a certain degree of “loss” of throughput may be associated with any transport activities or supplying the various substrates from one process chamber to another and for loading and unloading the substrates in the corresponding process chambers. The process capacity of the transport system 103 is adapted such that, upon completing the processing of a substrate within one of the process chambers 110, the required transport capabilities may substantially immediately be available without undue waiting time. On the other hand, when a maintenance activity is required for one of the process chambers 110, operation of the cluster tool 100 may be continued, however, at a reduced overall throughput, depending on the processing capacity of the non-productive process chamber.
FIG. 1c schematically illustrates the cluster tool 100 in the form of a deposition tool, in which, for instance, conductive materials may be deposited above the substrates 104. For instance, when forming complex metallization systems of semiconductor devices, typically a highly conductive metal, such as copper, may be used, which, however, may require specific manufacturing techniques and materials in order to obtain the required degree of reliability and electrical performance. For example, copper may readily diffuse in a plurality of well-established dielectric and semiconductive materials, such as silicon dioxide, silicon and the like, which, however, may result in non-predictable significant changes of the overall behavior of circuit elements, such as transistors and the like. For this and other reasons, typically, a conductive barrier material may be deposited on a patterned dielectric material prior to actually depositing the copper material on the basis of electrochemical deposition techniques. For example, tantalum, tantalum nitride and the like are well established conductive barrier materials which provide superior copper diffusion hindering effects and also enhanced mechanical adhesion and electromigration behavior of the corresponding copper metal regions. Furthermore, in well-established electrochemical deposition techniques, a seed material, such as a thin copper layer, may be deposited on the conductive barrier material to enhance the overall deposition behavior during the subsequent electrochemical deposition of the copper bulk material. Consequently, the deposition of the conductive barrier material, such as tantalum, tantalum nitride and the like, followed by the deposition of a copper seed material may be considered as correlated process steps, which may be performed in the cluster tool 100. Additionally, the surface of the patterned dielectric material may be appropriately treated prior to actually depositing the conductive barrier material, which may, for instance, include exposure to certain atmospheric conditions at elevated temperatures so as to promote out-gassing of undesired species, such as organic materials and the like. Since a pronounced waiting time between the de-gassing step and the actual deposition of the conductive barrier layer may have a significant influence on the finally-obtained process result, it is also advantageous to include the de-gassing step into the process tool 100 to minimize the time interval between cleaning the surface and actually depositing the conductive barrier material.
Thus, the cluster tool 100 is configured to perform the three process steps 51, S2, S3, i.e., in this example, a de-gas step, i.e., step 1, a first deposition step for providing a tantalum spacer material layer, i.e., step 2, and a final deposition step for forming a copper seed material, i.e., step 3. Furthermore, as previously discussed, the manufacturing processes may typically be performed on the basis of specific parameter settings, i.e., certain atmospheric conditions, predefined process times and the like, which, however, may vary depending on the type of semiconductor device to be produced. For example, if in some products an increased thickness of the copper seed material may be required, a respective recipe, for instance indicated as recipe A, may provide appropriately set deposition conditions, which may result in a specific deposition rate, while the overall process time may be selected in accordance with the required final layer thickness. Similarly, if superior de-gassing performance may be required for a certain type of semiconductor product, corresponding process conditions and/or the process time may be appropriately selected. Consequently, based on the various process parameters, the recipe A may result in corresponding process times of the process chambers 110. For example, the process step having the longest process time per process chamber, i.e., the process time divided by the number of available process chambers, may be considered as the bottleneck process step in the tool 100. Thus, this process step may define 100% of the overall capacity of the cluster tool 100. For example, according to recipe A, process step 2, i.e., the deposition of the tantalum-based material layer, may represent the bottleneck process and may thus define 100% of the overall capacity of the cluster tool 100. Furthermore, in the example shown, it may be assumed that equivalent process chambers, i.e., the chambers associated with a specific process step, may have the same capacity due to a very similar overall configuration. Consequently, in step 2, i.e., the bottleneck step, the process chambers 112A, 112B may each have a processing capacity of 50%. Furthermore, it may be assumed that in step 1 the recipe A may result in reduced process time compared to step 2, which may thus result in a processing capacity of 77% for each of the process chambers 110A, 110B. Similarly, in step 3, recipe A may result in an individual processing capacity of 79% for each of the chambers 113A, 113B. Consequently, upon failure of a process chamber in step 1, an overall capacity loss of 23% is obtained. Similarly, a downtime of one of the chambers 112A, 112B due to failure or maintenance may result in 50% of the total tool capacity. On the other hand, a downtime of any of the process chambers 113A, 113B may result in a total capacity loss of 21%. Thus, unless there is a failure in all process chambers of a single step, the cluster tool 100 may still remain in an operable state, however, at a reduced overall throughput.
As previously indicated, specific down times of the process chambers 110 may occur in a predictable manner, since regular maintenance may be required after processing a specific number of substrates, or after a certain degree of consumption of raw materials, and the like may be detected. Thus, by appropriately configuring the process chambers 110, it may be accomplished that corresponding maintenance activities for process chambers in one process step may not occur concurrently, thereby avoiding a complete down time of the cluster tool 100. As previously discussed, significant advantages may also be associated with configuring cluster tools on the basis of correlated process steps, nevertheless a reduction of overall throughput may be caused by predictable maintenance activities, which may thus contribute to enhanced production costs, since a corresponding throughput loss may have to be compensated for by initially providing an increased wafer processing capacity.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.